1. Field of the Invention
The invention relates to a display system, and more particularly, to a sync signal acquisition device so as to minimize a DC level drift due to process changes or temperature changes of either a Sync_on_Geen (SOG) circuit or a Sync_on_Luma (SOY) circuit.
2. Description of the Related Art
Conventionally, an analog front end device includes a SOG circuit, which extracts a composite sync signal based on a SOG signal, wherein the composite sync signal contains a horizontal sync (HS) signal and a vertical sync (VS) signal.
FIG. 1 is a schematic circuit diagram of a conventional SOG circuit. FIG. 2A is a waveform diagram of a SOG signal. FIG. 2B shows waveform diagrams of a SOG signal with its DC voltage level reconstructed, a composite sync signal HS+VS and a clamping signal CP.
Referring to FIG. 1, a SOG circuit 100 comprises a NMOS transistor 110, a resistor 120 and a comparator 130. A capacitor 140, usually installed in front of a node A in the SOG circuit 100, is configured to get rid of a DC voltage level of the SOG signal. The purpose of installing the SOG circuit 100 is to extract sync pulses from the SOG signal, i.e., extracting the negative pulse (or peak) depicted in FIG. 2A. An example of the simplest implementation is using a comparator. The voltage of the SOG signal may have positive and negative polarities (e.g., the voltage of the SOG signal ranging from −300 mV to 750 mV as shown in FIG. 2A), so the DC voltage level of an original SOG signal needs to be shifted before comparing with a comparing voltage VB2 by using the comparator 130. In other words, the entire voltage range of the SOG signal in this illustration is required to be equal to or greater than zero before comparison. Take FIG. 2B for example. The voltage of an original SOG signal ranges from −300 mV to 750 mV while the reconstructed voltage of the SOG signal ranges from 0V to 1.05V. At this moment, if the comparing voltage VB2 is set to a range of 0˜300 mV, then the composite sync signal HS+VS will be obtained easily. Wherein, a gate of the transistor 110 is coupled to a predetermined voltage VB1 (e.g., 0.5V), causing the transistor 110 to switch on as soon as a negative pulse of the SOG signal arrives. Accordingly, the potential of the node A is increasing, resulting in a rising potential of the composite sync signal HS+VS. Conversely, the transistor 110 is switched off while a non-negative voltage level of the SOG signal arrives at the SOG circuit 100. At this moment, the potential of the node A is going down due to a discharging voltage drop of the resistor 120, resulting in a falling potential of the composite sync signal HS+VS. The DC voltage level of the node A is finally settled after the balance of charging and discharging among the transistor 110, the capacitor 140 and the resistor 120. Therefore, the clamping mode in which the SOG circuit 100 operates is often called an “automatic clamping mode”.
In general, the interior of an integrated circuit is divided into a digital circuit and an analog circuit. Normally, there is no thermal drift in the digital circuit. By contrast, there is a thermal drift in the analog circuit. For example, there is process drift among integrated circuits, so its voltage varies according to the temperature and its frequency also varies according to the temperature. In applications of display system controllers (including the LCD controllers and the video decoders as mentioned above), users would like the display system to have the same characteristic both at start-up (usually at a lower temperature) and after warm-up (usually at a higher temperature), e.g., a consistent display color and a consistent optimum sampling phase of an analog to digital converter (ADC). It implies that the thermal drift is not allowed to occur in clampers, ADCs, a sync processor with clock generator, the SOG circuit, the SOY circuit and related circuits. Although the SOG circuit 100 is featured in a simple structure, a small size and low cost, the DC voltage level measured at the node A is not controlled easily and subject to drift due to process and temperature changes. This causes the reconstructed DC voltage level of the SOG signal to move vertically, resulting in a horizontally shifting composite sync signal HS+VS.